Assume that main memory accesses take 60 ns while L1 cache has the following features: L1 cache hit time: 0.5 ns, L1 cache miss rate: 8%. 2.1. What is the average memory access time if we only have L1 cache? 2.2. Now suppose we add an L2 cache with hit time as 5ns. What would the L2 miss rate need to be in order for the average memory access time to be improved compared with L1 cache only?

Answer :

Final answer:

The average memory access time with only L1 cache is 5.16 ns. To improve the average memory access time with the addition of L2 cache, the L2 miss rate needs to be less than 0.0026.

Explanation:

2.1. Average memory access time with L1 cache:

To calculate the average memory access time with L1 cache, we need to consider the hit rate and the miss penalty.

  1. The hit rate is the percentage of memory accesses that hit in the cache. In this case, the hit rate is 100% - 8% = 92%.
  2. The miss penalty is the time it takes to access main memory when there is a cache miss. In this case, the miss penalty is 60 ns - 0.5 ns = 59.5 ns.

Therefore, the average memory access time with L1 cache is:

Average memory access time = (Hit rate * L1 cache hit time) + (Miss rate * Miss penalty)

Average memory access time = (0.92 * 0.5 ns) + (0.08 * 59.5 ns) = 5.16 ns

2.2. L2 cache miss rate for improved average memory access time:

To improve the average memory access time compared with L1 cache only, we need to find the point where the L2 cache hit time plus the L2 miss rate times the L2 miss penalty is less than the average memory access time with L1 cache.

L2 cache hit time = 5 ns

Let's assume the L2 miss penalty is the same as the L1 miss penalty, which is 59.5 ns.

Therefore, we can calculate the L2 miss rate:

(L2 cache hit time) + (L2 miss rate) * (L2 miss penalty) < Average memory access time with L1 cache

5 ns + (L2 miss rate) * (59.5 ns) < 5.16 ns

L2 miss rate < (5.16 ns - 5 ns) / (59.5 ns) = 0.0026

L2 miss rate needs to be less than 0.0026 in order for the average memory access time to be improved compared with L1 cache only.

Learn more about Memory Access Time here:

https://brainly.com/question/31388776

#SPJ11